As a system in which an electronic device is formed on a substrate having a large area, it is known that a thin film transistor (TFT) is formed on the substrate to constitute an active matrix, a circuit and the like. In particular, it is expected that patterns of electrodes, semiconductors and the like are formed using printing technology by using an organic semiconductor, whereby an electronic device can be formed at a low temperature on a flexible substrate at low cost.
As a structure of an organic thin film transistor, a top gate bottom contact structure made by forming source and drain electrodes in a lower layer, forming a semiconductor layer thereon, forming a gate insulating layer, and further forming a gate electrode is a stagger structure where the gate electrode as well as the source and drain electrodes are arranged via the semiconductor, and hence it is considered that TFT characteristics are easily obtained.
When liquid crystals, electrophoretic particles, organic EL materials and the like are driven by an active matrix, it is necessary for the gate insulating layer to be opened and electrical connection made between the layers to one another, because the source and drain electrodes are present under the gate insulating layer in the top gate bottom contact structure. Furthermore, when an electronic circuit such as a shift register is formed, it is necessary to connect the gate electrode to the source and drain electrodes, and formation of a through hole in the gate insulating layer and the interlayer connection are required.
Examples of a method of forming the through hole in the insulating layer include a so-called lithography method in which a resist is exposed and developed and the layer is processed by using the resist as a mask, and a method in which a solvent is supplied by a needle or the like to locally dissolve the insulating layer, thereby accomplishing connection.
However, the lithography method has the problem that steps are complicated, which increases cost. In a technique described in the lithography method, a gate insulating layer is subjected to RIE (reactive ion etching) processing by use of a gate electrode as a mask, and hence it is necessary to form another electrode layer for the purpose of connecting a gate electrode layer to source and drain electrode layers. Furthermore, an edge portion of the gate electrode is common with a pattern edge of the gate insulating layer, and hence there is a problem in insulating properties between the gate electrode and the source and drain electrodes. Therefore, a countermeasure such as attachment of an additional insulating layer to cover a side surface is required. Furthermore, in the method where the solvent is supplied by the needle to dissolve the insulating layer, there is the problem that a fine opening cannot be made, and hence the method can only be applied to a rough pattern of a display section periphery or the like.